1. Field of the Invention
The present invention relates in general to the field of signal processing, and more specifically to a system and method that includes switching power converter control with triac-based leading edge dimmer compatibility.
2. Description of the Related Art
Power control systems often utilize a switching power converter to convert alternating current (AC) voltages to direct current (DC) voltages or DC-to-DC. Power control systems often provide power factor corrected and regulated output voltages to many devices that utilize a regulated output voltage. Switching power converters have been used as interfaces between triac-based dimmers and loads. The load can be virtually any load that utilizes converted power, such as one or more light emitting diodes (LEDs).
LEDs are becoming particularly attractive as main stream light sources in part because of energy savings through high efficiency light output and environmental incentives such as the reduction of mercury. LEDs are semiconductor devices and are driven by direct current. The lumen output intensity (i.e. brightness) of the LED approximately varies in direct proportion to the current flowing through the LED. Thus, increasing current supplied to an LED increases the intensity of the LED and decreasing current supplied to the LED dims the LED. Current can be modified by either directly reducing the direct current level to the white LEDs or by reducing the average current through duty cycle modulation.
Dimming a light source saves energy when operating a light source and also allows a user to adjust the intensity of the light source to a desired level. Many facilities, such as homes and buildings, include light source dimming circuits (referred to herein as “dimmers”). Power control systems with switching power converters are used to control constant current light sources. However, conventional dimmers, such as a triac-based dimmer, that are designed for use with resistive loads, such as incandescent light bulbs, often do not perform well when supplying a raw, phase modulated signal to a reactive load such as a switching power converter.
FIG. 1 depicts a power control system 100, which includes a switching power converter 102. Voltage source 101 supplies an AC supply voltage VIN to a triac-based dimmer 104. The voltage source 101 is, for example, a public utility, and the supply voltage VIN is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. Dimmer 104 receives the supply voltage VIN and generates a dimmer voltage VΦ—DIM. During a dimming period, dimmer 104 phase modulates the supply voltage VIN by introducing phase delays α into the beginning of each half cycle of dimmer voltage VΦ—DIM. “α” represents an amount of time between the beginning and leading edge of each half cycle of dimmer voltage VΦ—DIM. (“Introducing phase delays” is also referred to as “chopping”). The portion of the dimmer voltage VΦ—DIM having a phase delay α is referred to as the “dimming portion”. As subsequently described in more detail, the amount of phase delay α depends upon the amount of selected dimming. When dimmer 104 is not in a dimming period, i.e. dimmer 104 is not set to phase modulate the supply voltage VIN, the phase delay α is zero, and dimmer 104 simply passes the supply voltage VIN to full bridge diode rectifier 103. Rectifier 103 rectifies the dimmer voltage VΦ—DIM and supplies a rectified, time-varying, line input voltage VΦ—RECT to the switching power converter 102.
The power control system 100 includes a PFC and output voltage controller 114 to control power factor correction and regulate an output voltage VLINK of switching power converter 102. The PFC and output voltage controller 114 controls an ON (i.e. conductive) and OFF (i.e. nonconductive) state of switch 108 by varying a state of pulse width modulated control signal CS0. Switching between states of switch 108 regulates the transfer of energy from the rectified line input voltage VΦ—RECT through inductor 110 to capacitor 106. The inductor current iL ramps ‘up’ when the switch 108 is ON. The inductor current iL ramps down when switch 108 is OFF and supplies current iL to recharge capacitor 106. The time period during which inductor current iL ramps down is commonly referred to as the “inductor flyback time”. During the inductor flyback time, diode 111 is forward biased. Diode 111 prevents reverse current flow into inductor 110 when switch 108 is OFF. In at least one embodiment, the switching power converter 102 operates in discontinuous current mode, i.e. the inductor current iL ramp up time plus the inductor flyback time is less than the period of the control signal CS0. When operating in continuous conduction mode, the inductor current iL ramp-up time plus the inductor flyback time equals the period of control signal CS0.
The switch 108 is a field effect transistor (FET), such as an n-channel FET. Control signal CS0 is a gate voltage of switch 108, and switch 108 conducts when the pulse width of CS0 is high. Thus, the ‘ON time’ of switch 108 is determined by the pulse width of control signal CS0.
Capacitor 106 supplies stored energy to load 112. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage VLINK, as established by PFC and output voltage controller 114. As load conditions change, the output voltage VLINK changes. The PFC and output voltage controller 114 responds to the changes in output voltage VLINK and adjusts the control signal CS0 to restore a substantially constant output voltage VLINK as quickly as possible. Power control system 100 includes a small, filter capacitor 115 in parallel with switching power converter 102 to filter any high frequency signals from the input voltage VΦ—RECT.
The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, PFC and output voltage controller 114 attempts to control the inductor current iL SO that the average inductor current iL is linearly and directly related to the line input voltage VΦ—RECT. Prodić, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of PFC and output voltage controller 114.
In at least one embodiment, the values of the pulse width and duty cycle of control signal CSo depend on sensing two signals, namely, the input voltage VΦ—RECT and the capacitor voltage/output voltage VLINK. PFC and output voltage controller 114 receives the input voltage VΦ—RECT and the output voltage VLINK respectively via a wide bandwidth current loop 116 and a slower voltage loop 118. The input voltage VΦ—RECT is sensed from node 120 between the diode rectifier 103 and inductor 110. The output voltage VLINK is sensed from node 122 between diode 111 and load 112. The current loop 116 operates at a frequency fc that is sufficient to allow the PFC and output voltage controller 114 to respond to changes in the line input voltage VΦ—RECT and cause the inductor current iL to track the input voltage VΦ—RECT to provide power factor correction. The current loop frequency is generally set to a value between 20 kHz and 130 kHz. The voltage loop 118 operates at a much slower frequency fv, typically 10-20 Hz. By operating at 10-20 Hz, the voltage loop 118 regulates slow variations in the output voltage VLINK due to AC line voltage fluctuations in amplitude.
FIG. 2 (labeled prior art) depicts a triac-based power and dimming system 200 that includes a triac-based dimmer 202. Potentiometer 204 conducts current I to charge capacitor 206. During a dimming period, diac 208 blocks current to triac 210 until capacitor 206 reaches a breakover voltage of diac 208. When capacitor 206 reaches the breakover voltage, diac 208 conducts, and capacitor 206 discharges through diac 208. When capacitor 206 discharges, capacitor 206 supplies a current to triac 210, and triac 210 conducts. The time between when the supply voltage VIN crosses zero and when the triac 210 conducts represents the phase delay α of dimmer voltage VΦ—DIM. The resistance of potentiometer 204 sets the value of phase delay α. The resistance R of potentiometer 204 and capacitance C of capacitor 206 form an RC time constant that determines a phase delay α (FIG. 3) of dimmer voltage VDIM. Increasing R increases the phase delay α, and decreasing R decreases the phase delay α. When R is decreased sufficiently, the phase delay α is essentially zero, and, thus, VΦ—DIM=VIN. The value of R is set by potentiometer 204. The value of C and the range of R are matters of design choice.
When the phase delay α is zero, dimmer 202 stops dimming. In at least one embodiment, when dimmer 202 is dimming and the supply voltage VIN reaches 0, diac 208 and triac 210 stop conducting. When dimming, the alternating conduction/nonconduction of triac 210 modulates the phase of the supply voltage VIN. Resistor 214, capacitor 216, and inductor 218 provide high frequency rejection for dimmer 202.
Referring to FIGS. 1 and 2, controller 114 operates switch 108 to provide power factor correction so that input current iL tracks changes in input voltage VΦ—RECT. In at least one embodiment, when the input voltage VΦ—RECT approaches a zero crossing, a very low input resistance is presented. Presenting a very low input resistance to a triac-based dimmer 104 can cause the triac 210 to turn ON and OFF multiple times during a single half cycle of input voltage VΦ—RECT. As discussed in more detail below, oscillations in the conduction of triac 210 during a single half cycle of input voltage VΦ—RECT can cause problems, such as flicker in a lamp when load 112 includes a lamp.
FIG. 3 depicts a series of ideal voltage waveforms 300 that represent two respective cycles of waveforms present in an ideal power and dimming system 200 during two dimming periods. Referring to FIGS. 1, 2, and 3, supply voltage VIN is a sine wave depicted with two exemplary cycles 302 and 304. Dimmer 104 generates the phase modulated voltage VΦ—DIM by chopping each half cycle of supply voltage VIN to ideally generate one, leading edge phase delay α1 for each respective half cycle of cycle 306. The phase delays α of the phase modulated signal VΦ DIM increase as the dimming level increases, i.e. as phase delays α increase, less power is delivered to load 112. If load 112 is a lamp, dimming level increases correspond to decreases in brightness of the lamp. Half cycle 308 indicates a longer phase delay α2 corresponding to a decrease in dimming level. The exemplary leading edge phase delays α1 and α2 represent the elapsed time between a beginning of a half cycle and a leading edge of dimmer voltage VΦ—DIM. The cycles 310 and 312 of rectified input voltage VΦ—RECT have the same respective phase delays α1 and α2 as the phase modulated signal VΦ—DIM. The phase delayed portions of voltages VΦ—DIM and VΦ—RECT represented by α1 and α2 are also referred to as the “dimming portion” of voltages VΦ—DIM and VΦ—RECT.
As previously mentioned, conventional dimmers, such as triac-based dimmer 202, that are designed for use with resistive loads, such as incandescent light bulbs, often do not perform well when supplying a phase modulated signal VΦ—DIM to a reactive load such as switching power converter 102. For example, when supplying a reactive load, the dimmer 202 can miss generating phase delays in some cycles of phase modulated signal VΦ—DIM and can generate ripple during the phase delays. Exemplary problems with at least one conventional triac-based dimmer when used with a reactive load are described in Rand et al., “Issues, Models and Solutions for Triac Modulated Phase Dimming of LED Lamps”, June, 2007, pages 1398-1404 of Power Electronics Specialists Conference, 2007. PESC 2007, published by the Institute of Electrical and Electronic Engineers, ISBN 978-1-4244-0655-5. Thus, although the rectified input voltage VΦ—RECT ideally has one phase delay per cycle during dimming, when driving a reactive load, such as a switching power converter 102, problems such as missing phase delays and multiple phase delays α in a single half cycle of the rectified input voltage VΦ—RECT exist.
Although minor ripple may be present during the dimming portion of the input voltage VΦ—RECT, the multiple phase delays α during a single half cycle of input voltage VΦ—RECT cause significant interruptions in the initial phase delay α of the input voltage VΦ—RECT. In at least one embodiment, triac 210 (FIG. 2) turning ON and OFF multiple times during a single half cycle of input voltage VΦ—RECT causes the significant interruptions in the initial phase delay α of the input voltage VΦ—RECT. When triac 210 (FIG. 2) turns ON and OFF multiple times during a dimming portion of a half cycle of input voltage VΦ—RECT, the input voltage VΦ—RECT increases and decreases multiple times during the dimming portion of the half cycle of input voltage VΦ—RECT. Multiple oscillations of the input voltage VΦ—RECT during a half cycle of the input voltage VΦ—RECT can cause problems such as flicker of a lamp load.
Conventional solutions to the problem of interfacing a triac-based dimmer with a reactive switching power converter 102 involve adding additional components to, for example, discharge the filter capacitor 115 during the dimming portion of dimmer voltage VΦ—DIM.
FIGS. 4A and 4B (collectively referred to as FIG. 4) depict an LED driver circuit 400 available from Supertex, Inc. of Sunnyvale, Calif., USA. LED driver circuit 400 represents one embodiment of light source driver circuit 106. The LED driver circuit 400 is described in more detail in Supertex design note DN-H05 available from Supertex, Inc. The LED driver circuit 400 includes two extra circuits, damper circuit 402 and bleeder circuit 404 to provide compatibility with a dimmer, such as dimmer 104. According to DN-H05, the damper circuit 402 provides damped charging of the driver's input filter circuit at P16. The damper circuit 402 provides resistive damping to prevent AC line input current oscillations due to a sudden rise of an AC line voltage, such as the edges of dimmer voltage VΦ—DIM. The bleeder circuit 404 provides a nominal 1 kohm load to a rectified AC line at P21 to suppress a voltage rise at the input capacitors C21-C23 due to leakage current of diac 208 and triac 210 (FIG. 2) during dimming portions of dimmer voltage VΦ—DIMwhich could otherwise cause flicker of a lamp driven by LED driver circuit 400.
FIG. 5 depicts a unity power factor LED lamp driver 500, which represents one embodiment of light source driver circuit 106. The LED lamp driver 500 is described in more detail in Supertex application note AN-H52 available from Supertex, Inc. LED lamp driver 500 includes damping circuitry 502 to add a load to dimmer 104 during dimming portions of the dimmer voltage VΦ—DIM. The damping circuitry 502 includes a bleeder resistor RBL that is connected by transistor M2 during the dimming portions of dimmer voltage VΦ—DIM to lamp driver 500. When transistor M2 conducts, the bleeder resistor RBL provides an added load to the AC line at VIN to dampen the dimmer voltage VΦ—DIM during dimming portions. Adding an extra transistor M2 and resistor RBL increases the system cost of lamp driver 500.
It would be desirable to reduce or eliminate the extra components of LED driver circuit 400 and LED lamp driver 500 that provide a load to dimmer 104 during the dimming portion of dimmer voltage VΦ—DIM. It would also be desirable to reduce or eliminate the power consumption of resistive loads added by LED driver circuit 400 and LED lamp driver 500 that provide a load to dimmer 104 during the dimming portion of dimmer voltage VΦ—DIM.